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EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown
PRODUCT FEATURES
GENERAL DESCRIPTION The EMC2102 is an SMBus, closed-loop, RPM-based fan controller/driver with hardware (HW) thermal shutdown and reset controller. The EMC2102 is packaged in a thermally enhanced, compact, 5x5, 28pin lead-free RoHS compliant QFN package. The EMC2102 utilizes Beta Compensation and Resistance Error Correction (REC) to accurately monitor three external temperature zones. These features allow great accuracy for CPU substrate thermal diodes on multiple process geometries as well as with discrete diode-connected transistors. Both Beta Compensation and REC can be disabled on the EMC2102 to maintain accuracy when monitoring AMD thermal diodes. The EMC2102 includes a closed-loop RPM based Fan Control Algorithm that integrates a linear fan driver capable of sourcing 600mA of current. The fan control algorithm is designed to work with fans that operate up to 16,000 RPMs. The EMC2102 provides a stand-alone HW thermal shutdown block. The HW thermal shutdown logic can be configured for a few common configurations based on the strapping level of the SHDN_SEL pin on the PCB. The HW thermal shutdown point can be set in 1C increments by using a discrete resistor divider implemented on the TRIP_SET pin. The EMC2102 also provides 5V supply `power good' function with a threshold of 4.5V. This function is provided on the RESET# pin.
Datasheet FEATURES Beta Compensation Allows Accurate Temperature Measurement on 65nm CPU/GPUs Closed-Loop RPM Based Fan Controller
-- Accepts External Clock Source To Achieve 2% Accuracy
Integrated Linear Fan Driver
-- 600mA Drive Capability
HW Thermal Shutdown (SYS_SHDN#)
-- 1C Incremental Set Points For Thermal Shutdown -- Cannot be disabled by software
Provides Reset Function (RESET#) On 5V Supply Three Remote Thermal Zones
-- 1C Accuracy (60C to 100C) -- 1C Resolution
Resistance Error Correction On Thermal `Diode' Channels
-- Eliminates Temperature Offset Due To Series Resistance From PCB Traces And Thermal `Diode'
Thermally Enhanced, 28-pin, 5x5 QFN Lead-free RoHS Compliant Package Operates From Single 3.0 - 3.6V Supply
-- 5V Supply For Linear Fan Driver
Software Configurable ALERT# Signal For Diode Fault, Fan Stall Or System Warning APPLICATIONS Notebook Computers Desktop Computers Embedded Applications
SMSC EMC2102
DATASHEET
Revision 1.95 (10-19-06)
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
ORDER NUMBER:
EMC2102-DZK FOR 28-PIN QFN LEAD-FREE ROHS COMPLIANT PACKAGE (ADDRESS - 011_1101)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.95 (10-19-06)
DATASHEET
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SMSC EMC2102
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 Pin Layout for EMC2102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Description for EMC2102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 16 16 17 17
Chapter 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Programming the RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 TACH Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 FAN_MODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 32.768KHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Side Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Overcurrent Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Thermal Shutdown (TSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 TRIP_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Internal HW_SHDN Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 21 21 23 23 23 25 25 25 26 26 26 26 28 28 29 30
5.2 5.3
Stalled Fan 23
5.4 5.5 5.6 5.7
5.8
Chapter 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 6.2 6.3 6.4 6.5 6.6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 34 34 35 36
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RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Step Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37 37 38 39 40 40 41 42 43 43 44 44 44 45 45
Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Appendix A TACH Reading Table - 2000 RPM Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Appendix B TACH Reading Table - 500RPM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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SMSC EMC2102
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
List of Tables
Table 2.1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5.2 FAN_MODE Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.3 CLK_SEL Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.4 SHDN_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.1 EMC2102 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.2 Temperature data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.4 Critical/Thermal Shutdown Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.6 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.7 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6.8 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.9 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.10 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.11 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.12 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6.13 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.14 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.15 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 6.16 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 6.17 Fan Control Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.18 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.19 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.20 Fan TACH Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.21 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.22 Fan Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.23 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.24 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.25 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.26 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.27 Example TACH Reading for Specific Fan Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 6.28 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 6.29 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
List of Figures
Figure 1.1 Figure 2.1 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 7.1 EMC2102 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EMC2102 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EMC2102 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 EMC2102 Critical/Thermal Shutdown Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 HW_SHDN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5V Reset Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . 46
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Chapter 1 Block Diagram
THERMTRIP# SYS_SHDN#
SHDN_SEL
VDD_3V
VDD_5V
RESET#
TRIP_SET DP1 DN1 DP2 DN2 DP3 DN3 Internal Temp Diode External Temp Diodes
Critical / Thermal Shutdown Logic
Reset Generator
SMBus Slave Protocol
SMCLK SMDATA ALERT#
Analog Mux 11 bit ADC
Ext Temp Limit Registers
POWER_OK
Ext. Temp Registers
Bandgap Reference
Voltage Reading
8-bit DAC
Automatic Fan Control Algorithms
Voltage -> Temperature Converison
Register Set and Logic
High Side Fan Driver
TACH Monitor
FAN_MODE
FAN (2)
TACH
VDD_5V (2)
Figure 1.1 EMC2102 Block Diagram
SMSC EMC2102
CLK_SEL
CLK_IN
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Chapter 2 Pinout
2.1 Pin Layout for EMC2102
28
27
26
25
24
23
VDD_3V DN1 DP1 DN2 DP2 DN3 DP3
1 2 3 4 5 6 7 FAN_MODE 10 TRIP_SET 11 SYS_SHDN# 12 THERMTRIP# 13 POWER_OK 14 8 SHDN_SEL 9 EMC2102 5 x 5 QFN
22 21 N/C 20 GND 19 ALERT# 18 CLK_IN 17 CLK_SEL 16 RESET# 15 N/C
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Figure 2.1 EMC2102 Pin Diagram
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SMDATA
VDD_5V
VDD_5V
SMCLK
TACH
FAN
FAN
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RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
2.2
Pin Description for EMC2102
Table 2.1 Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NAME VDD_3V DN1 DP1 DN2 DP2 DN3 DP3 N/C SHDN_SEL FAN_MODE TRIP_SET SYS_SHDN# THERMTRIP# POWER_OK N/C RESET# CLK_SEL CLK_IN ALERT# GND N/C SMDATA SMCLK
FUNCTION Supply Connection of 3.3V. Negative (cathode) Analog Input for External Diode 1. Positive (anode) Analog Input for External Diode 1. Negative (cathode) Analog Input for External Diode 2. Positive (anode) Analog Input for External Diode 2. Negative (cathode) Analog Input for External Diode 3. Positive (anode) Analog Input for External Diode 3. Not internally connected. Determines HW Shutdown temperature channel (see Table 5.4.) Selects power-up default for fan drive setting. Voltage input to determine HW Shutdown threshold temperature Active low Critical System Shutdown output Active low Critical temperature limit signal from the CPU or chipset. Active high power good input. Not internally connected. Active low reset output. Selects internal oscillator or external clock. 32.768KHz clock input. Active low interrupt. GND connection. Not internally connected. SMBus data input/output. SMBus clock input. Power AIO AIO AIO AIO AIO AIO N/A DIT DIT AI OD (5V) IP DI (5V) N/A DO DI (5V) DI (5V) OD (5V) Power N/A
TYPE
DIOD (5V) - requires external upllup resistor DI (5V) - requires external pull-up resistor
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Table 2.1 Pin Description (continued) PIN 24 NAME VDD_5V FUNCTION 5V supply input for the linear fan driver. Both VDD_5V pins should be connected to same 5V supply. Linear fan drive signal. Both FAN pins should be connected together. Linear fan drive signal. Both FAN pins should be connected together. 5V supply input for the linear fan driver. Both VDD_5V pins should be connected to same 5V supply. Input from the tachometer pin of the fan. Power TYPE
25 26 27
FAN FAN VDD_5V
AO AO Power
28
TACH
DI (5V)
The pin type are described in detail below. All pins labelled with (5V) are 5V tolerant.: Power - this pin is used to supply power to the device. DI - Digital Input - this pin is used as a digital input. This pin is 5V tolerant. AI - Analog Input - this pin is used as an input for analog signals.. AO - Analog Output - this pin is used as an output for analog signals. AIO - Analog Input / Output - this pin is used as an I/O for analog signals. DO - Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current and doesn't require a pull-up resistor. DIOD - Open Drain Digital Input / Output - this pin is used as an digital I/O. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD - Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. DIT - Tri-stated Digital Input - this pin is a digital input that supports 3 logic levels at the input: logic high, logic low, or high impedance (open). IP - Digital Input - this pin has an internal 30uA pull-up current to VDD_3V
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Chapter 3 Electrical Specifications
3.1 Absolute Maximum Ratings
Table 3.1 Absolute Maximum Ratings Voltage on VDD_5V Pins and 5V tolerant pins (see Table 2.1) Voltage on VDD_3V pin Voltage on FAN pins Voltage on any other pin to GND Package Power Dissipation Junction to Ambient (JA) Note 3.3 Operating Ambient Temperature Range Operating Die Temperature Range Storage Temperature Range ESD Rating, All Pins, HBM -0.3 to 6.5 -0.3 to 4 -0.3 to VDD_5V + 0.3 -0.3 to VDD_3V + 0.3 0.9 up to TA = 85C Note 3.2 37 0 to 85 0 to 125 -55 to 150 2000 V V V V W C/W C C C V
These ratings are absolute maximum values. Exceeding these values or operating at these values for an extended period of time may cause permanent damage to the device. Note 3.1 Note 3.2 Note 3.3 All voltages are relative to ground. The Package Power Dissipation specification assumes a thermal via design consisting of four 20mil vias connected to the ground plane with a 3.1mm x 3.1mm thermal landing. Junction to Ambient (JA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the JA is approximately 60C/W including localized PCB temperature increase.
3.2
Electrical Specifications
Table 3.2 Electrical Specifications VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP DC Power
MAX
UNIT
CONDITIONS
3.3V Supply Voltage 5V Supply Voltage Supply Current from VDD_3V pin Supply Current from VDD_5V pin
VDD_3V VDD_5V IDD3 IDD5
3 4.6
3.3 5 500 200
3.6 5.5 750
V V uA uA Fan Driver enabled Fan Driver enabled
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Table 3.2 Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
External Temperature Monitors Temperature Accuracy 1 1 Temperature Resolution Diode decoupling capacitor CFILTER 1 2200 1.5 3 C C C pF Connected across external 2N3904 diode or AMD diode (Note 3.5) Connected across CPU or GPU thermal diode (Note 3.5) Series resistance in DP and DN lines 60C < TDIODE < 100C 30C < TDIE < 85C (Note 3.4) 0C < TDIODE < 125C, 0C < TDIE < 115C (Note 3.4)
470 Resistance Error Corrected RSERIES 100 Internal Temperature Monitor Temperature Accuracy Temperature Resolution 3 1 Reset Generator Reset Voltage Hysteresis Time Delay VRESET 4.3 4.4 100 220 High Side Fan Driver Output High Voltage from 5V supply Fan Drive Current Overcurrent Limit DC Short Circuit Current Limit Short circuit delay Output Capacitive Load ESR on CLOAD VOH_5V ISOURCE IOVER ISHORT 1500 800 VDD_5 V - 0.4 600 4.5
pF Ohm
C C
(Note 3.4 )
V mV ms
VDD_5V rising edge 3V < VDD_3V < 3.6V
VRESET
tRESET
V mA mA mA
ISOURCE = 600mA, VDD_5V = 5V
Momentary Current drive at startup for < 2 seconds Sourcing current, Thermal shutdown not triggered, FAN_OUT = 0V
tDFS CLOAD RESR 0
2 100 2
s uF Ohm
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Table 3.2 Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
RPM Based Fan Controller TACH Range TACH Setting Accuracy TACH 480 1 5 16000 2 7.5 RPM % % External oscillator 32.768kHz Internal Oscillator 40C < TDIE < 100C
TACH TACH
Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSDTH TSDHYST 150 50 SMBus and Digital I/O pins Output High Voltage Output Low Voltage Note 3.4 Note 3.5 VOH VOL VDD _3V 0.4 0.5 V V 2 mA current drive 4mA current sink C C
TDIE refers to the internal die temperature and may not match TA due to self heating of the device. The internal temperature sensor will return TDIE. Contact SMSC for Application Notes and guidelines when measuring GPU processor diodes and CPU processor diodes.
3.3
SMBus Electrical Specifications
Table 3.3 SMBus Electrical Specifications VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0C to 85C Typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High Voltage Input Low Voltage Input High/Low Current Input Capacitance Output Low Sink Current VIH VIL IIH / IIL CIN -1 5 4 SMBus Timing Clock Frequency Spike Suppression
SMSC EMC2102
2.0 0.8 1
V V uA pF mA SMDATA = 0.5V
fSMB tSP
10
400 50
13
kHz ns
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Table 3.3 SMBus Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0C to 85C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC Bus free time Start to Stop Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load SYMBOL tBUF tSU:STA tSU:STP tHD:DAT tSU:DAT tLOW tHIGH tFALL tRISE CLOAD MIN 1.3 0.6 0.6 0.6 0.6 1.3 0.6 300 300 400 6 72 TYP MAX UNITS us us us us us us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns per bus line CONDITIONS
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Chapter 4 System Management Bus Interface Protocol
The EMC2102 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported, however the EMC2102 will not stretch the clock signal.
.
TLOW
THIGH
THD:STA
TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDTA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 4.1 SMBus Timing Diagram The EMC2102 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is not in full compliance. All of the below protocols use the convention in Table 4.1. Table 4.1 Protocol Format DATA SENT TO DEVICE # of bits sent DATA SENT TO THE HOST # of bits sent
4.1
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 4.2: Table 4.2 Write Byte Protocol SLAVE ADDRESS 7 REGISTER ADDRESS 8 REGISTER DATA 8
START 1
WR 1
ACK 1
ACK 1
ACK 1
STOP 1
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4.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3. Table 4.3 Read Byte Protocol
START
SLAVE ADDRESS
W R
ACK
Register Address
ACK
START
Slave Address
RD
ACK
Register Data
NACK
STOP
1
7
1
1
8
1
1
7
1
1
8
1
1
4.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4. Table 4.4 Send Byte Protocol SLAVE ADDRESS 7 REGISTER ADDRESS 8
START 1
WR 1
ACK 1
ACK 1
STOP 1
4.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5. Table 4.5 Receive Byte Protocol SLAVE ADDRESS 7
START 1
RD 1
ACK 1
REGISTER DATA 8
NACK 1
STOP 1
4.5
Alert Response Address
The ALERT# output can be used as a processor interrupt or as an SMBALERT. When it detects that the SMBALERT pin is asserted, the host will send the Alert Response Address (general address of 000_1100b) on the bus. All devices with active interrupts will respond with their client address as shown in Table 4.6.
..
Table 4.6 Alert Response Address Protocol ALERT RESPONSE ADDRESS 7
START 1
RD 1
ACK 1
DEVICE ADDRESS 8
NACK 1
STOP 1
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The EMC2102 will respond to the ARA command if the ALERT# pin has been asserted but will not immediately release the ALERT# pin. The ALERT# pin is released under the following conditions. 1. The Interrupt Status Registers are read and the error condition has been removed. 2. The specific error condition is masked from asserting the ALERT# pin.
4.6
SMBus Address
The EMC2102-1 is addressed on the SMBus as 011_1101b. Attempting to communicate with the EMC2102 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents.
4.7
SMBus Time-out
The EMC2102 includes an SMBus time-out feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface.
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Chapter 5 General Description
The EMC2102 monitors three external temperature channels. Two of the external temperature channels can employ both Beta Compensation and Resistance Error Correction for use with thermal diodes while the third channel is hardwired to measure a discrete diode connected NPN or PNP transistor. The temperature data is available over a standard 2-wire serial interface using SMBus read commands. The temperature monitoring is described in more detail in Section 5.1, "Temperature Monitoring". The EMC2102 integrates a closed-loop RPM based Fan Control Algorithm. A host writes the desired fan speed into a register of the EMC2102 via the SMBus and the integrated fan controller will maintain the fan at the desired speed using fan speed feedback from the TACH output from a 3-wire fan. The fan control algorithm controls an integrated 5V, 600mA, linear fan driver. The fan control algorithm functionality is described in more detail in Section 5.3, "RPM based Fan Control Algorithm" The EMC2102 provides the system with a hardware based critical/thermal shutdown function. This critical/thermal shutdown function integrates critical signals from both the CPU and power supply and the analog circuitry to monitor a specific temperature channel based on the system configuration. The critical/thermal shutdown temperature threshold is configured on the PCB through a simple discrete resistor divider. The Critical/Thermal Shutdown function is described in more detail in Section 5.7, "Critical/Thermal Shutdown". An example of a typical system configuration for the EMC2102 is provided in Figure 5.1.
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3.3V
VDD_3V VDD_5V
5V
EMC2102 SMBCLK SMBDATA ALERT
CPU
SMCLK SMDATA ALERT# TACH FAN DP1 DN1
3.3V
TACHOMETER
FAN VCC
Thermal diode
GPU Thermal diode
DP2 DN2
DIMM
DP3 DN3
Thermal diode
3.3V
CLK_SEL CLK_IN
32.768KHz Clock 3.3V
3.3V
FAN_MODE SHDN_SEL TRIP_SET
3.3V
SYS_SHDN THERMTRIP POWER_OK
SYS_SHDN# THERMTRIP# POWER_OK
RESET#
RESET
Figure 5.1 EMC2102 System Diagram
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5.1
Temperature Monitoring
External diode channels one and two can be configured to monitor either discrete thermal diodes or a CPU / GPU thermal diode. External diode channel three is always configured to monitor a discrete diode-connected transistor (such as a 2N3904) or an AMD thermal diode. Each channel can enable the Resistance Error Correction functionality and external diode channels one and two can adjust the Beta Compensation settings (disabling it if desired). The disabling of these features is only recommended in two situations: 1. An AMD thermal diode is being monitored. The AMD thermal diode is physically a 2-terminal diode and will not function with either Beta Compensation or Resistance Error Correction. Because of this, when an EMC2102 temperature channel is interfacing an AMD thermal diode, both Beta Compensation and Resistance Error Correction must be disabled. 2. A discrete diode connected transistor (such as 2N3904) is used. In this configuration, Beta Compensation must be disabled, but Resistance Error Correction should remain enabled.
5.1.1
Resistance Error Correction
The EMC2102 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC2102 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path.
5.1.2
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC2102 corrects for this beta variation to eliminate any error which would normally be induced.
5.1.3
Fault Queue
To avoid spurious interrupts and Critical/Thermal Trip events induced by thermal spikes and noise injection, the selected Thermal / Critical Shutdown Temperature channel (see Section 5.7.2) is filtered through a fault queue. This fault queue requires that a user-defined number of consecutive out-of-limit errors be recorded before it will cause an interrupt or trigger the Critical/Thermal trip event. The fault queue only applies to the measurement channels that will cause the SYS_SHDN# pin to be asserted including any software configured channels (see Section 5.7). In addition, the fault queue applies to all enabled channels simultaneously and will trigger the SYS_SHDN# pin if there are the desired number of consecutive measurements with any or all channels exceeding their corresponding limits.
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5.2
Fan Control Modes of Operation
The EMC2102 has two modes of operation for the High Side Fan Driver. They are: 1. Manual Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see Section 6.12) will instantly update the fan drive. The Manual Mode is enabled by clearing the EN bit in the Fan Configuration Register (see Section 6.13). Whenever the Manual Mode is enabled the current drive will be changed to what was last written into the Fan Driver Setting Register. Setting the drive value to 00h will disable the High Side Fan Driver for lower power operation. 2. Using RPM based Fan Control Algorithm - in this mode of operation, the user determines a target TACH count and the drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. Table 5.1 Fan Controls Active for Operating Mode MANUAL MODE Fan Driver Setting (read / write) EDGES[1:0] Valid TACH Count TACH Reading ALGORITHM Fan Driver Setting (read only) EDGES[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive Valid TACH Count TACH Target TACH Reading
5.3
RPM based Fan Control Algorithm
The EMC2102 includes a RPM based Fan Control Algorithm that controls an integrated linear High Side Fan Driver. This fan control algorithm automatically approaches and maintains the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. Figure 5.2 shows a simple flow diagram of the RPM based Fan Control Algorithm operation. The desired TACH count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan revolution. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000RPMs, then the user would input the hexidecimal equivalent of 655 (29h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs (see Equation [3] in Section 6.19).
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The EMC2102's RPM based Fan Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2102 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768KHz clock source or with it's own internal 32.768KHz oscillator depending on the required accuracy.
S e t T A C H T a rge t C ou n t
M e a su re F an S pe e d
S p in U p R e qu ired ? No
Yes
P erform S pin U p R o u tin e
M ain tain F a n D riv e
Y es
TACH R e a ding = TACH T a rge t?
No
Yes
TACH R e a ding < TACH T a rge t?
No
R am p R a te C on tro l
R e d u ce F a n D rive
In cre a se F a n D rive
Figure 5.2 RPM based Fan Control Algorithm
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5.3.1
Programming the RPM based Fan Control Algorithm
The RPM based Fan Control Algorithm powers-up enabled and active. The following registers control the algorithm. The EMC2102 fan control registers are preloaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. 1. Set the Valid TACH Count Register to the minimum TACH count that indicates the fan is spinning. 2. Set the Spin Up Configuration Register to the spin up level and Spin Time desired. 3. Set the Fan Step Register to the desired step size. 4. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 5. Set the Update Time, and Edges options in the Fan Configuration Register. 6. Set the TACH Target Register to the desired TACH count.
5.3.2
TACH Measurement
In both modes of operation, the TACH measurement will work normally. Any TACH count that is higher than the Valid TACH Count (see Section 6.17) will flag a stalled fan and trigger an interrupt. The EMC2102 includes a TACH measurement circuit. The TACH signal must be valid at all times to ensure proper operation. The TACH measurement circuitry is programmable to detect the fan speed of a variety of fan configurations and architectures including 1-pole, 2-pole (default), 3-pole, and 4-pole fans.
APPLICATION NOTE: The TACH measurement works independently of the drive settings. If the device is put into manual mode and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the TACH measurement may signal a Stalled Fan condition and assert an interrupt.
5.3.2.1
Stalled Fan
If the TACH counter exceeds the user-programmable Valid TACH Count setting then it will flag the fan as stalled and trigger an interrupt. If the RPM based Fan Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid TACH level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. Whenever the Manual Mode is enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 6.21) to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Manual Mode, whenever the drive value is changed from 00h, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Manual Mode, whenever the TACH count exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. When the RPM based Fan Control Algorithm, the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
5.3.3
Spin Up Routine
The EMC2102 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. During Manual Mode, the Spin Up Routine will not control the fan drive settings under any conditions.
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When the RPM based Fan Control Algorithm is running, the Spin Up Routine is initiated under the following conditions: APPLICATION NOTE: When the device is operating in manual mode, the FAN_SPIN status bit may be set if the fan drive is set at a level that is lower than the fan can operate (including zero drive). If the FAN_SPIN interrupt is unmasked, then this condition will trigger an errant interrupt. 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 6.18 and Section 6.17). 2. At power-up if the FAN_MODE setting is `1' or `open' indicating 75% drive or 60% drive respectively. If the FAN_MODE setting is `0' indicating 0% drive, then the Spin Up Routine is not initiated until another condition is met. 3. The RPM based Fan Control Algorithm is started and the FAN_MODE setting is `0' indicating 0% drive prior to algorithm control. 4. The RPM based Fan Control Algorithm's measured TACH count is greater than the Valid TACH Count. When the Spin Up Routine is operating, the fan driver is set to full scale for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set a a user defined level (60% or 75% drive). After the Spin Up Routine has finished, the EMC2102 measures the TACH. If the measured TACH count is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 5.3 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above.
100%
60% or 75% Fan Step New Target Count Algorithm controlled drive Prev Target Count = FFh
1/4 of Spin Up Time
Spin Up Time
Update Time
Target Count Changed
Check TACH
Figure 5.3 Spin Up Routine
Target Count Reached
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5.3.4
FAN_MODE Pin
The FAN_MODE pin is used to determine the fan driver output levels at power-up before the EMC2102 has been programmed. After power-up, the fan driver will be set at the selected drive until the RPM based Fan Control Algorithm is started or disabled. The level on the pin determines the function as shown in Table 5.2. Table 5.2 FAN_MODE Pin Functions FAN_MODE 0 open 1 FUNCTION Fan Driver set at 0% drive Fan Driver set at 60% drive after Spin Up Routine Fan Driver set at 75% drive after Spin Up Routine
5.3.5
32.768KHz Clock Source
The EMC2102 allows the user to choose between supplying an external 32.768KHz clock or use of the internal 32.768KHz oscillator to measure the TACH signal. This clock source is used by the RPM based Fan Control Algorithm to calculate the current fan speed. This fan controller accuracy is directly proportional to the accuracy of the clock source. To enable the external clock source, the CLK_SEL pin must be pulled to VDD_3V at power-up (see Table 5.3). The CLK_SEL pin is must be in a known state at all times (either pulled high or pulled low) and is latched upon power-up. Table 5.3 CLK_SEL Pin Functions CLK_SEL 0 1 Internal oscillator used External clock used FUNCTION
5.4
Watchdog Timer
The EMC2102 contains an internal Watchdog Timer. Once the device has powered up the watchdog timer monitors the bus traffic for signs of activity. The Watchdog Timer starts when the VDD_5V supply has reached its operating point. The Watchdog Timer only starts immediately after power-up and once it has been triggered or deactivated will not restart. If four (4) seconds elapse without the system host programming the device, then the following will occur: 1. The WATCH status bit will be set. 2. The High Side Fan Driver will be set to full scale drive. It will remain at full scale drive until one of the two conditions listed below are met. If the Watchdog Timer is triggered, the following two operations will disable the timer and return the device to normal operation. 1. Writing the RPM based Fan Control Algorithm TACH Target Register will disable the Watchdog Timer regardless of the value. If a value is written that is greater than the Valid TACH Count Register setting (other than FFh), the fan drive setting will be set based on the FAN_MODE pin
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condition (0%, 60% or 75% drive). If a value of FFh is written, then the fan driver will be disabled until a valid setting is written. 2. Disabling the RPM based Fan Control Algorithm by clearing the EN bit will disable the Watchdog Timer. The fan driver will be set to the programmed setting written in the Fan Driver Setting Register. Writing any other configuration registers will not disable the Watchdog Timer. If the VDD_5V supply drops below the reset threshold, then the Watchdog Timer will be stopped but not reset.
5.5
High Side Fan Driver
The EMC2102's fan controller integrates a 5V, 600mA, linear high side fan driver to directly drive a 5V fan. By fully integrating the linear fan driver, the typical requirement for the discrete pass device and other external linearization circuitry is completely eliminated. The linear fan driver is driven by an 8-bit DAC providing better than 20mV resolution between steps.
5.5.1
Overcurrent Limit
The High Side Fan Driver contains circuitry to allow for significant overcurrent levels to accommodate transient conditions on the FAN pins. The overcurrent limit is dependent upon the output voltage with the limit dropping as the voltage nears 0V. If the fan driver current detects a short-circuit condition for longer than 2 seconds, then the I_SHORT status bit is set and an interrupt generated. Additionally, the fan driver will be disabled (by setting the drive level to 00h). In both Manual Mode and when using the RPM based Fan Control Algorithm, the device will attempt to restart the fan after a time equal to the spin-up time programmed in the Fan Spin Up Configuration Register (see Section 6.14). If the High Side Fan Driver is configured to operate in Manual Mode, when it attempts to restart the fan after a overcurrent condition, it will set the Fan Drive Setting Register to the most recently written value (prior to the overcurrent condition). If the High Side Fan Driver is configured to use the RPM based Fan Control Algorithm, it will invoke the Spin Up Routine described in Section 5.3.3. If the overcurrent condition persists, the fan driver will continue to attempt to restart the fan until the overcurrent condition is removed or the High Side Fan Driver is disabled by setting the TACH Target to FFh (when using the RPM based Fan Control Algorithm) or by writing the Fan Setting Register to a value of 00h (when operating in Manual Mode)
5.6
Internal Thermal Shutdown (TSD)
The EMC2102 contains an internal thermal shutdown circuit that monitors the internal die temperature. If the die temperature exceeds the Thermal Shutdown Threshold (see Table 3.2), then the following will occur: 1. The High Side Fan Driver is disabled. It will remain disabled until the internal temperature drops below the threshold temperature minus 50C. 2. The TSD Status bit will be set and the ALERT pin asserted. This signal cannot be masked. 3. The SYS_SHDN pin is asserted.
5.7
Critical/Thermal Shutdown
The EMC2102 provides a hardware Critical/Thermal Shutdown function for systems. Figure 5.4 is a block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function in the EMC2102 consists of both analog and digital functions. It accepts digital inputs from the CPU
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(THERMTRIP#) and power supply (POWER_OK) and configuration information from the fixed states of the SHDN_SEL pins as described in Section 5.7.2. In addition, each of the temperature limits can be configured to act as inputs to the Critical / Thermal Shutdown independent of the hardware shutdown operation. The analog portion of the Critical/Thermal Shutdown function monitors a specific remote temperature channel (configured with the SHDN_SEL pin). This measured temperature is then compared with the TRIP_SET point. This TRIP_SET point is created by the system designer with a simple resistor divider and is discussed in detail in Section 5.7.1.
Critical Shutdown Logic
H/W Set Sensor SYS1 - SYS3 Configuration Register SMBus Traffic Temperature Conversion and Limit Registers SW_SHDN
S/W Set Sensor
S/W Set Sensor
`0' or `open' H/W Critical Sensor PIN Decode Temperature Conversion `1' SHDN_SEL
3.3V HW_SHDN TRIP_SET Voltage Conversion Thermal_SHDN Thermal Shutdown THERMTRIP# ThermTrip_ SHDN POWER_OK SYS_SHDN#
From CPU / Chipset From the Power Supply
ThermTrip# Power_OK ThermTrip_SHDN 0 0 0 0 1 1 1 0 0 1 1 0
Figure 5.4 EMC2102 Critical/Thermal Shutdown Block Diagram
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5.7.1
TRIP_SET
The EMC2102's TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets the Thermal Shutdown temperature. The system designer creates a voltage level at this input through a simple resistor divider between the 3.3V supply and GND. This input voltage is valid between 0V and 1.5V which corresponds to Thermal Shutdown temperature setpoints between 75C and 106C as described in the following equation. T TRIP - 75 TRIP_SET Pin Voltage = --------------------------21
Where: TTRIP is the desired trip point temperature TRIPSET is the voltage on the TRIP_SET pin
[1]
5.7.2
SHDN_SEL Pin
The EMC2102 has one `strappable' input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown. This pin has 3 possible states and is monitored and decoded by the EMC2102 at power-up. The three possible states are 0 (tied to GND), 1 (tied to 3.3V) or High-Z (open). The states of this pin determine which remote temperature channel and configuration is used by the Critical/Thermal Shutdown function. The different configurations of SHDN_SEL pin are described in Table 5.4 A channel that is configured via the SHDN_SEL pin for the Critical/Thermal Shutdown is locked and none of the configuration registers associated with it can be updated via the SMBus. The other two temperature channels, however, are still configurable via the SMBus. Table 5.4 SHDN_SEL Pin Configuration REMOTE CHANNEL INPUT TO THERMAL SHUTDOWN 1
SHDN_SEL 0
FUNCTION NAME Intel Mode
CRITICAL/THERMAL SHUTDOWN DETAILS Channel 1 is configured and locked with both Beta Compensation and Resistance Error Correction enabled which is optimized for an Intel thermal diode. Channel 3 is configured and locked with Resistance Error Correction enabled which is optimal for interfacing a discrete diodeconnected NPN transistor. The Critical/Thermal Shutdown function will not assert SYS_SHDN# based on a temperature channel. This does not include software configured inputs (see Section 6.4)
High-Z
Diode Mode
3
1
Disabled,
NA
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5.7.3
Internal HW_SHDN Signal
The HW_SHDN output from the Critical/Thermal Shutdown Monitor is a logical indicator of the temperature state of the chosen external diode channel. HW_SHDN is an internal signal routed as an input to the Thermal / Critical Shutdown logic. The HW_SHDN output is set to logic `1' when the indicated temperature exceeds the temperature threshold (TP) established by the TRIP_SET input pin (as shown in Figure 5.5) for a number of consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the temperature drops below TP, then it will be set to a logic `0' state.
Temperature Exceeds TP TP
Measurements End
Temperature drops to TP or below
Temperature not defined HW_SHDN After 4th measurement, HW_SHDN set
Figure 5.5 HW_SHDN Operation
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5.8
5V Reset Controller
The EMC2102 also provides a `power-good' reset controller for the system's 5V supply rail. The reset controller will set the RESET# pin to a logic `0' after power-up and set the RESET# pin to a logic `1' 220ms after the VDD_5V supply rises above its threshold voltage (see Table 3.2). If the VDD_5V supply drops below the reset threshold, then the RESET# pin will be set to `0' immediately.
VDD_5V
Reset Threshold (4.4V) Reset Threshold hysteresis (4.3V) VDD_3V or pull-up voltage 220ms
RESET#
Figure 5.6 5V Reset Controller Timing
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Chapter 6 Register Set
6.1 Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect. Table 6.1 EMC2102 Register Set REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Temperature Registers
LOCK
PAGE
00h 01h 02h 03h 04h
R R R R R
Internal Temp Reading External Diode 1 Temp Reading External Diode 2 Temp Reading External Diode 3 Temp Reading Critical/Thermal Shutdown Temperature
Stores the integer data of the Internal Temp Reading Stores the integer data of External Diode 1 Stores the integer data of External Diode 2 Stores the integer data of External Diode 3 Stores the calculated Critical/Thermal Shutdown temperature high limit derived from the voltage on TRIP_SET. Configuration and control
00h 00h 00h 00h 7Fh
No No No No No
Page 33
Page 33
Page 34
20h
R/W
Configuration
Configures the Thermal / Critical Shutdown masking options and software lock Configures the conversion rate Stores the status bits for temperature channels Stores the status bits for the thermal shutdown and RPM based Fan Control Algorithm Controls the masking of interrupts on all maskable channels Diode Configuration
80h
SWL
Page 34 Page 35 Page 36 Page 37 Page 37
21h 22h 23h
R/W R-C R-C
Conversion Rate Interrupt Status Register 1 Interrupt Status Register 2 Interrupt Mask Register
02h 80h 00h
SWL No No
24h
R/W
10h
No
30h
R/W
External Diode 1 Beta Configuration External Diode 2 Beta Configuration External Diode REC Configuration
Configures the beta compensation settings for External Diode 1 Configures the beta compensation settings for External Diode 2 Configures the Resistance Error Correction functionality for all external diodes
03h
SWL Page 38
31h
R/W
03h
SWL
32h
R/W
07h
SWL
Page 39
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Table 6.1 EMC2102 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Temperature Limit Registers
LOCK
PAGE
41h 42h 43h
R/W R/W R/W
External Diode 1 Temp High Limit External Diode 2 Temp High Limit External Diode 3 Temp High Limit
High limit for External Diode 1 High limit for External Diode 2 High limit for External Diode 3 Fan Control Registers
55h (+85C) 55h (+85C) 55h (+85C)
SWL SWL SWL Page 40
51h
R/W
Fan Driver Setting
Always displays the most recent fan driver input setting. If the RPM based Fan Control Algorithm is disabled, allows direct user control of the fan driver. Sets configuration values for the RPM based Fan Control Algorithm Sets the configuration values for Spin Up Routine of the High Side Fan Driver Sets the maximum change per update for the High Side Fan Driver Sets the minimum drive value for the High Side Fan Driver Holds the minimum TACH value that indicates the fan is spinning properly Holds the target TACH count for the fan Holds the TACH count for the fan Revision Registers
00h
No Page 40
52h 53h 54h 55h 56h 57h 58h
R/W R/W R/W R/W R/W R/W R
Fan Configuration Fan Spin Up Configuration Fan Step Fan Minimum Drive Fan Valid TACH Count TACH Target TACH Reading
CBh 01h 10h 80h F5h FAh FFh
No SWL SWL SWL SWL No No
Page 41 Page 42 Page 43 Page 43 Page 44 Page 44 Page 44
FDh FFh
R R
Product ID Revision
Stores the unique Product ID Revision
14h 00h
No No
Page 45 Page 45
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD_3V supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect.
6.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set.
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6.2
Temperature Data Registers
Table 6.2 Temperature data Registers
ADDRESS 00h 01h 02h 03h
REGISTER Internal Diode External Diode 1 External Diode 2 External Diode 3
B7 Sign Sign Sign Sign
B6 64 64 64 64
B5 32 32 32 32
B4 16 16 16 16 8 8 8 8
B3
B2 4 4 4 4
B1 2 2 2 2 1 1 1 1
B0
DEFAULT 00h 00h 00h 00h
The temperature measurement range is from 0C to +191C. The data format can be selected between pure 2's complement format which displays data from 0C to +127C, or in offset 2's complement format that displays data over the entire data range. The temperature format is shown below: Table 6.3 Temperature Data Format 2'S COMPLEMENT FORMAT TEMPERATURE (C) Diode Fault <= 0 1 63 64 65 127 128 (Note 6.1) 190 191 Note 6.1 BINARY 1000 0000 0000 0000 0000 0001 0011 1111 0100 0000 0100 0001 0111 1111 0111 1111 0111 1111 0111 1111 80h 00h 01h 3Fh 40h 41h 7Fh 7Fh 7Fh 7Fh HEX OFFSET 2'S COMPLEMENT FORMAT BINARY 1000 0000 1100 0000 1100 0001 1111 1111 0000 0000 0000 0001 0011 1111 0100 0000 0111 1110 0111 1111 80h C0h C1h FFh 00h 01h 3Fh 40h 7Eh 7Fh HEX
In 2's complement format, any temperature above +127C will be displayed as +127C
If the High Side Fan Driver is active, then self-heating of the large current drive device will affect the internal temperature reading. Therefore, it is not recommended that the Internal temperature channel be used to monitor the ambient air temperature.
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6.3
Critical/Thermal Shutdown Temperature Register
Table 6.4 Critical/Thermal Shutdown Temperature Register
ADDRESS 04h
REGISTER Critical/Therm al Shutdown Temperature
B7 Sign
B6 64
B5 32
B4 16 8
B3
B2 4
B1 2 1
B0
DEFAULT 7Fh (+127C)
The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents of the register reflect the calculated temperature based on the TRIP_SET voltage. This register is updated at the end of every monitoring cycle based on the current value of TRIP_SET. The register value reflects the exact threshold temperature. The data format will match the selected format of the temperature data registers as shown in Table 6.3.
6.4
Configuration Register
Table 6.5 Configuration Register
ADDRESS 20h
REGISTER Configuration
B7
B6
B5 SYS3
B4 SYS2
B3 SYS1
B2 FORMAT
B1 -
B0 LOCK
DEFAULT 80h
QUEUE[1:0]
The Configuration Register controls the basic functionality of the EMC2102. The bits are described below. The Configuration Register is software locked. Bit 7-6 - QUEUE[1:0] - determines how many consecutive out-of-limit errors must occur on the hardware selected and software enabled temperature channels before the SYS_SHDN# pin is asserted (see Table 5.2). The queue applies to all enabled channels simultaneously and will trigger the SYS_SHDN# pin if there are four consecutive measurements with any or all channels exceeding their corresponding limits. Table 6.6 Fault Queue QUEUE1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF FAULTS 1 2 4 (default) 8
Bit 5 - SYS3 - enables the high temperature limit for the External Diode 3 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7). `0' (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally.
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`1' - the External Diode 3 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 4 - SYS2 - enables the high temperature limit for the External Diode 2 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7). `0' (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. `1' - the External Diode 2 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 3 - SYS1 - enables the high temperature limit for the External Diode 1 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7). `0' (default) - the External Diode 1channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. `1' - the External Diode 1 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 2 - FORMAT - determines the data format that is displayed in the Temperature Data Registers. The data format for the Critical Thermal Shutdown Threshold Register will not be changed. If the temperature data format is changed, the limit register values must be changed to match the newer format. `0' (default) - the temperature data will be in standard 2's complement format. `1' - the temperature data will be in offset 2's complement format. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them.
6.5
Conversion Rate Register
Table 6.7 Conversion Rate Register
ADDRESS 21h
REGISTER Conversion Rate -
B7 -
B6 -
B5 -
B4 -
B3 -
B2
B1
B0
DEFAULT 02h
CONV[1:0]
The Conversion Rate Register controls the conversion rate of the temperature monitoring as well as the fault queue. The Conversion Rate Register is software locked. Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases.
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Table 6.8 Conversion Rate CONV[1:0] 1 0 0 1 1 0 0 1 0 1 CONVERSION RATE 1 / sec 2 / sec 4 / sec (default) 8 / sec
6.6
Interrupt Status Register 1
Table 6.9 Interrupt Status Register 1
ADDRESS 22h
REGISTER Interrupt Status Register 1
B7 RESET
B6 TSD
B5 ERR3
B4 TRD3
B3 ERR2
B2 TRD2
B1 ERR1
B0 TRD1
DEFAULT 80h
The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits are set to a logic `1' (other than the RESET pin) then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. The bits that cause the ALERT# pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. Bit 7 - RESET - this bit mirrors the output of the RESET# pin. When the RESET# pin is set to a logic `0' (indicating that the VDD_5V supply is lower than the reset threshold), this bit is set to a logic `1' as well. This bit will not cause the ALERT# pin to be asserted. Bit 6 - TSD - this bit is asserted `1' if there is a thermal shutdown condition. This bit cannot be masked. Bit 5 - ERR3 - this bit is asserted `1' if there is a diode fault on External Diode 3. Bit 4 - TRD3 - this bit is asserted `1' if the External Diode 3 Temperature measurement exceeds the high limit. Bit 3 - ERR2 - this bit is asserted `1' if there is a diode fault on External Diode 2. Bit 2 - TRD2 - this bit is asserted `1' if the External Diode 2 Temperature measurement exceeds the high limit. Bit 1 - ERR1 - this bit is asserted `1' if there is a diode fault on External Diode 1. Bit 0 - TRD1 - this bit is asserted `1' if the External Diode 1 Temperature measurement exceeds the high limit.
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6.7
Interrupt Status Register 2
Table 6.10 Interrupt Status Register 2
ADDRESS 23h
REGISTER Interrupt Status Register 2
B7 PWROK
B6 THERM
B5 HWS
B4 -
B3 WATCH
B2 FAN_S PIN
B1 FAN_S TALL
B0 I_SHO RT
DEFAULT 00h
The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits (except the PWROK, THERM, and HWS bits) are asserted then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. Bit 7 - PWROK - this bit is set if the POWER_OK pin is set to a logic `1' state. When this bit is set, it will not cause the ALERT# pin to be asserted. Bit 6 - THERM - this bit is set if the THERMTRIP# pin is set to a logic `0' state. When this bit is set, it will not cause the ALERT# pin to be asserted however will coincide with SYS_SHDN# pin being asserted. The THERMTRIP# pin can only cause the SYS_SHDN# pin to be asserted if the POWER_OK pin is set to a logic `1' (see Figure 5.4). Bit 5 - HWS - this bit is set if the internal HW_SHDN signal is set (see Section 5.7.3) based on the TRIP_SET voltage and the SHDN_SEL pin conditions. When this bit is set, it will not cause the ALERT# pin to be asserted however will coincide with SYS_SHDN# pin being asserted. Bit 3 - WATCH - this bit is asserted `1' if the Watchdog Timer circuit does not detect the fan being programmed within 4 seconds after power-up. This bit cannot be masked. Bit 2 - FAN_SPIN - this bit is asserted `1' if the Spin up Routine for Fan cannot detect a valid TACH within its maximum time window. This bit can be masked from asserting the ALERT# pin. Bit 1 - FAN_STALL - this bit is asserted `1' if the TACH measurement on fan detects a stalled fan. This bit can be masked from asserting the ALERT# pin. Bit 0 - I_SHORT - this bit is asserted `1' if the High Side Fan Driver circuit detects a short circuit condition. This bit cannot be masked.
6.8
Interrupt Mask Register
Table 6.11 Interrupt Mask Register
ADDRESS 24h
REGISTER Interrupt Mask -
B7
B6 -
B5
B4 SPIN_ MASK
B3 STALL_ MASK
B2 EXT3_ MSK
B1 EXT2_ MSK
B0 EXT1_ MSK
DEFAULT 10h
The Interrupt Mask Register controls the masking for each temperature channel and the TACH monitor. When a channel is masked, it will not cause the ALERT# pin to be asserted when an error condition is detected. Bit 4 - SPIN_MASK - masks the FAN_SPIN bit from asserting the ALERT# pin. `0' - the FAN_SPIN bit will assert the ALERT# pin if set in the Interrupt Status Register 2. `1' - (default) - the FAN_SPIN bit will not assert the ALERT# pin though will still update the Interrupt Status Register 2 normally. Bit 3 - STALL_MASK - masks the FAN_STALL bit from asserting the ALERT# pin.
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`0' (default) - the FAN_STALL bit will assert the ALERT# pin if set in the Interrupt Status Register 2. `1' - the FAN_STALL bit will not assert the ALERT# pin though will still update the Interrupt Status Register 2 normally. Bit 2 - EXT3_MASK - masks the ERR3 and TRD3 bits from asserting the ALERT# pin. `0' (default) - the ERR3 and TRD3 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR3 and TRD3 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally. Bit 1 - EXT2_MASK - masks the ERR2 and TRD2 bits from asserting the ALERT# pin. `0' (default) - the ERR2 and TRD2 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR2 and TRD2 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally. Bit 0 - EXT1_MASK - masks the ERR1 and TRD1 bits from asserting the ALERT# pin. `0' (default) - the ERR1 and TRD1 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR1 and TRD1 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally.
6.9
Beta Configuration Registers
Table 6.12 Beta Configuration Registers
ADDRESS 30h
REGISTER External Diode 1 Beta Configuration External Diode 2 Beta Configuration -
B7 -
B6 -
B5 -
B4 -
B3
B2
B1
B0 03h
DEFAULT
BETA1[2:0]
31h
-
-
-
-
-
BETA2[2:0]
03h
The Beta Configuration Registers control advanced temperature measurement features for each External Diode channel. The Beta Configuration Registers are software locked. When the External Diode 1 Channel is selected by the SHDN_SEL pin to be the hardware shutdown input channel (see Table 5.4), the External Diode 1 Beta Configuration Register becomes read only. Writing to the register will have no affect and reading from it will always reflect the current beta settings (05h). For the External Diode 3 Channel, the beta compensation setting is fixed at `111b' indicating that the beta compensation is disabled. Bit 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation circuitry can compensate for. The Beta Configuration Registers activate the Beta Compensation circuitry if any value besides 111 is written. The register should be set with a value corresponding to the lowest expected value of beta for the PNP transistor being used as a temperature sensing device. See Table 6.13 for supported beta ranges. The default setting is calibrated for 65nm CPU's. For 90nm CPU's the optimal beta setting is 04h.
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When the Beta Compensation circuitry is disabled, the diode channels will function with default current levels and will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904 transistor or AMD thermal diode. All of the Beta Configuration Registers are Software Locked. Table 6.13 Beta Compensation Look Up Table BETAX[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0.1111 0.1765 0.25 0.333 (default) 0.4285 1.0 2.333 Disabled MINIMUM BETA
6.10
REC Configuration Register
Table 6.14 REC Configuration Register
ADDRESS 32h
REGISTER REC Configuration
B7 -
B6 -
B5 -
B4 -
B3 -
B2 REC3
B1 REC2
B0 REC1
DEFAULT 07h
The REC Configuration Register determines whether Resistance Error Correction is used for each external diode channel. The REC Configuration Register is software locked. If either the External Diode 1 channel or External Diode 3 channel is selected by the SHDN_SEL pin to be the hardware shutdown input channel (see Table 5.4), then the corresponding RECx bit will be locked. Writing to the bit will have no affect and reading from it will always report the current setting. Bit 2 - REC3 - Controls the Resistive Error Correction functionality of External Diode 3 `0' - the REC functionality for External Diode 3 is disabled `1' (default) - the REC functionality for External Diode 3 is enabled. Bit 1 - REC2 - Controls the Resistive Error Correction functionality of External Diode 1 `0' - the REC functionality for External Diode 2 is disabled `1' (default) - the REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Controls the Resistive Error Correction functionality of External Diode 1 `0' - the REC functionality for External Diode 1 is disabled `1' (default) - the REC functionality for External Diode 1 is enabled.
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6.11
Temperature Limit Registers
Table 6.15 Temperature Limit Registers
ADDRESS 41h 42h 43h
REGISTER External Diode 1 High Limit External Diode 2 High Limit External Diode 3 High Limit
B7 Sign Sign Sign
B6 64 64 64
B5 32 32 32
B4 16 16 16 8 8 8
B3
B2 4 4 4
B1 2 2 2 1 1 1
B0
DEFAULT 55h (+85C) 55h (+85C) 55h (+85C)
The EMC2102 contains high limits for all temperature channels.If any particular temperature channel exceeds the high limit then the appropriate status bit is set. Each temperature channel software limit can be individually enabled to assert the SYS_SHDN# pin if the temperature exceeds this limit. All Temperature Limit Registers are Software Locked.
6.12
Fan Driver Setting Register
Table 6.16 Fan Driver Setting Register
ADDRESS 51h
REGISTER Fan Driver Setting
B7 128
B6 64
B5 32
B4 16 8
B3
B2 4
B1 2
B0 1
DEFAULT 00h
The Fan Driver Setting Register always displays the current setting of the High Side Fan Driver. If the RPM based Fan Control Algorithm is disabled, this register can be written to manually control the fan driver (manual mode). See Section 5.2. If this register is written to while the RPM based Fan Control Algorithm is active, it will not affect the current output drive. The value that is written will be retained however and used as the current drive if the RPM based Fan Control algorithm is disabled. Reading from this register will report the current fan speed setting regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. The contents of the register represent the weighting of each bit in determining the final output voltage. The output voltage is given by Equation [2].
VALUE FAN_OUT = -------------------- x VDD_5V 255
[2]
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6.13
Fan Configuration Register
Table 6.17 Fan Control Configuration Register
ADDRESS 52h
REGISTER FAN Configuration
B7 EN
B6 LIMIT2K -
B5
B4
B3
B2
B1
B0
DEFAULT CBh
EDGES[1:0]
UPDATE[2:0]
The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used for the High Side Fan Driver. Bit 7 - EN - enables the RPM based Fan Control Algorithm. `0' - the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' (default) - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bit 6 - LIMIT2K - Adjusts the range of reported and programmed TACH count values. `0' - the range of reported and programmable TACH values allows for a minimum speed of approximately 500 RPM with reduced resolution to report lower speed values. `1' (default) - the range of reported and programmable TACH values allows for a minimum speed of approximately 2000 RPM with increased resolution to report higher speed values. Bit 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate TACH measurement, the minimum number of poles may be increased, however the TACH measurement will be artificially higher than expected as denoted in the Effective TACH multiplier. Additionally, some fans have more than 2-poles and therefore require more edges to be measured as shown in the Number of Fan Poles The EDGES[1:0] bits are shown in Table 6.18. Table 6.18 Minimum Edges for Fan Rotation EDGES[1:0] 1 0 0 1 1 0 1 0 1 0 MINIMUM TACH EDGES 3 5 7 9 NUMBER OF FAN POLES 1 pole 2 poles (default) 3 poles 4 poles EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0.6 1 1.4 1.8
Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 6.19.
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Table 6.19 Update Time UPDATE[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms 800ms 1200ms 1600ms
6.14
Fan Spin Up Configuration Register
Table 6.20 Fan TACH Configuration Register
ADDRESS 53h
REGISTER Fan Spin Up Configuration -
B7 -
B6 -
B5 -
B4 -
B3
B2 LEVEL
B1
B0
DEFAULT 01h
SPINUP_TIM E [1:0]
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine used by the RPM based Fan Control Algorithm. The Fan Spin Up Configuration Register is software locked. Bit 2 - LEVEL - determines the spin up level that is used whenever the Spin Up Routine is initiated after power-up `0' (default) - the spin up level will be 60% of full scale. `1' - the spin up level will be 75% of full scale. Bit 1 -0 - SPINUP_TIME[2:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 5.3.3). If a valid TACH is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM based Fan Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 6.21. Table 6.21 Spin Time SPINUP_TIME[1:0] 1 0 0 0 0 1 TOTAL SPIN UP TIME 250 ms 500 ms (default)
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Table 6.21 Spin Time (continued) SPINUP_TIME[1:0] 1 1 1 0 0 1 TOTAL SPIN UP TIME 1 sec 2 sec
6.15
Fan Step Register
Table 6.22 Fan Step Register
ADDRESS 54h
REGISTER Fan Step -
B7 -
B6
B5 32
B4 16
B3 8 4
B2 2
B1 1
B0
DEFAULT 10h
The Fan Step Register, along with the Update Time, controls the ramp rate of the fan driver response calculated by the RPM based Fan Control Algorithm. The value of the register represents the maximum step size the fan driver will take between update times (see Section 6.13). The Fan Step Register setting can be translated to a maximum voltage step as shown in Equation [2]. If the necessary fan driver delta is larger than the Fan Step, it will be capped at the Fan Step setting and updated every Update Time ms. The Fan Step Register is software locked.
6.16
Fan Minimum Drive Register
Table 6.23 Minimum Fan Drive Register
ADDRESS 55h
REGISTER Fan Minimum Drive
B7 128
B6 64
B5 32
B4 16
B3 8 4
B2 2
B1 1
B0
DEFAULT 80h
The Fan Minimum Drive Register stores the minimum drive setting for the RPM based Fan Control Algorithm. The RPM based Fan Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed is set at FFh (see Section 6.18) During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Register is software locked.
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6.17
Valid TACH Count Register
Table 6.24 Valid TACH Count Register
ADDRESS 56h
REGISTER Valid TACH Count
LIMIT2K `0' `1'
B7 2048 512
B6 1024 256
B5 512 128
B4 256 64
B3 128 32
B2 64 16
B1 32 8
B0 16 4
DEFAULT F5h
The Valid TACH Count Register stores the maximum TACH count to indicate that the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [3] for translating the count to an RPM. If the TACH count exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. If a TACH Target Count is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count Register is software locked.
6.18
TACH Target Register
Table 6.25 TACH Reading Registers
ADDRESS 57h
REGISTER TACH Target
LIMIT2K `0' `1'
B7 2048 512
B6 1024 256
B5 512 128
B4 256 64
B3 128 32
B2 64 16
B1 32 8
B0 16 4
DEFAULT FAh
The TACH Target Register holds the target TACH count that is maintained by the RPM based Fan Control Algorithm. If the algorithm is enabled, setting the Fan Target to FFh will immediately disable the High Side Fan Driver. Setting the Fan Target to any other value will cause the algorithm to invoke the Spin Up Routine after which it will function normally.
6.19
TACH Reading Register
Table 6.26 TACH Reading Register
ADDRESS 58h
REGISTER Fan TACH
LIMIT2K `0' `1'
B7 2048 512
B6 1024 256
B5 512 128
B4 256 64
B3 128 32
B2 64 16
B1 32 8
B0 16 4
DEFAULT FFh
The TACH Reading Register contents describe the current TACH setting of the fan. The data represents the fan speed as the number of 32.768kHz clock periods that occur for a single revolution of the fan.
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Equation [3] shows the simplified translation of TACH Reading Register count to RPM assuming a 2pole fan, measuring 5 edges.
sec 11RPM = --------------------- ( revolutions ) x 32768 -------- x 60 --------- min sec COUNT
COUNT = TACH Reading Register . value (in decimal)
[3]
Table 6.27 Example TACH Reading for Specific Fan Speeds TACH READING REGISTER F6h FFh (Note 6.2) 3Dh F5h 0Fh 3Dh 07h 1Eh Note 6.2 LIMIT2K 0 1 0 1 0 1 0 1 RPM 500 500 2000 2000 8000 8000 16000 16000
If the LIMIT2K bit is set, the minimum fan speed that can be measured is approximately 1950RPM. Any fan speed lower than this value will be reported as FFh.
6.20
Product ID Register
Table 6.28 Product ID Register
ADDRESS FDh
REGISTER Product ID Register (EMC2102-1) 0
B7 0
B6 0
B5 1
B4 0
B3 1
B2
B1 0 0
B0
DEFAULT 14h
The Product ID Register contains a unique 8 bit word that identifies the product.
6.21
Revision Register
Table 6.29 Revision Register
ADDRESS FFh
REGISTER Revision 0
B7 0
B6 0
B5 0
B4 0
B3 0
B2
B1 0 0
B0
DEFAULT 00h
The Revision Register contains a 8 bit word that identifies the die revision.
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Chapter 7 Package Drawing
Figure 7.1 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters
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Appendix A TACH Reading Table - 2000 RPM Range
Table A.1 TACH Reading Table - Limit2K = `1'
DEC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 HEX 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C RPM 491520 245760 163840 122880 98304 81920 70217 61440 54613 49152 44684 40960 37809 35109 32768 30720 28913 27307 25869 24576 23406 22342 21370 20480 19661 18905 18204 17554
Table A.1 TACH Reading Table - Limit2K = `1'
DEC 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 HEX 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C
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Table A.1 TACH Reading Table - Limit2K = `1'
DEC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 HEX 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C RPM 8058 7928 7802 7680 7562 7447 7336 7228 7123 7022 6923 6827 6733 6642 6554 6467 6383 6302 6222 6144 6068 5994 5922 5851 5783 5715 5650 5585 5523 5461 5401 5343
RPM 16949 16384 15855 15360 14895 14456 14043 13653 13284 12935 12603 12288 11988 11703 11431 11171 10923 10685 10458 10240 10031 9830 9638 9452 9274 9102 8937 8777 8623 8474 8331 8192
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Table A.1 TACH Reading Table - Limit2K = `1'
DEC 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 HEX 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C RPM 5285 5229 5174 5120 5067 5016 4965 4915 4867 4819 4772 4726 4681 4637 4594 4551 4509 4468 4428 4389 4350 4312 4274 4237 4201 4165 4130 4096 4062 4029 3996 3964
Table A.1 TACH Reading Table - Limit2K = `1'
DEC 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 HEX 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C
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Table A.1 TACH Reading Table - Limit2K = `1'
DEC 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 HEX 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC RPM 3131 3111 3091 3072 3053 3034 3015 2997 2979 2961 2943 2926 2908 2891 2874 2858 2841 2825 2809 2793 2777 2761 2746 2731 2716 2701 2686 2671 2657 2643 2628 2614
SMSC EMC2102
RPM 3932 3901 3870 3840 3810 3781 3752 3724 3696 3668 3641 3614 3588 3562 3536 3511 3486 3461 3437 3413 3390 3367 3344 3321 3299 3277 3255 3234 3213 3192 3171 3151
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Table A.1 TACH Reading Table - Limit2K = `1'
DEC 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 HEX BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC RPM 2601 2587 2573 2560 2547 2534 2521 2508 2495 2482 2470 2458 2445 2433 2421 2409 2398 2386 2374 2363 2352 2341 2329 2318 2308 2297 2286 2276 2265 2255 2244 2234
Table A.1 TACH Reading Table - Limit2K = `1'
DEC 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 HEX DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC
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Table A.1 TACH Reading Table - Limit2K = `1'
DEC 253 254 255 HEX FD FE FF RPM 1943 1935 Disabled
RPM 2224 2214 2204 2194 2185 2175 2165 2156 2146 2137 2128 2119 2110 2101 2092 2083 2074 2065 2057 2048 2040 2031 2023 2014 2006 1998 1990 1982 1974 1966 1958 1950
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Appendix B TACH Reading Table 500RPM Range
Table B.1 TACH Reading Table - Limit2K = `0'
DEC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 HEX 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B RPM 122880 61440 40960 30720 24576 20480 17554 15360 13653 12288 11171 10240 9452 8777 8192 7680 7228 6827 6467 6144 5851 5585 5343 5120 4915 4726 4551
Table B.1 TACH Reading Table - Limit2K = `0'
DEC 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 HEX 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B
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Table B.1 TACH Reading Table - Limit2K = `0'
DEC 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 HEX 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B RPM 2048 2014 1982 1950 1920 1890 1862 1834 1807 1781 1755 1731 1707 1683 1661 1638 1617 1596 1575 1555 1536 1517 1499 1480 1463 1446 1429 1412 1396 1381 1365 1350
SMSC EMC2102
RPM 4389 4237 4096 3964 3840 3724 3614 3511 3413 3321 3234 3151 3072 2997 2926 2858 2793 2731 2671 2614 2560 2508 2458 2409 2363 2318 2276 2234 2194 2156 2119 2083
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Table B.1 TACH Reading Table - Limit2K = `0'
DEC 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 HEX 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B RPM 1336 1321 1307 1293 1280 1267 1254 1241 1229 1217 1205 1193 1182 1170 1159 1148 1138 1127 1117 1107 1097 1087 1078 1069 1059 1050 1041 1033 1024 1016 1007 999
Table B.1 TACH Reading Table - Limit2K = `0'
DEC 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 HEX 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B
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Table B.1 TACH Reading Table - Limit2K = `0'
DEC 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 HEX 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB RPM 788 783 778 773 768 763 759 754 749 745 740 736 731 727 723 719 714 710 706 702 698 694 690 686 683 679 675 671 668 664 661 657
RPM 991 983 975 968 960 953 945 938 931 924 917 910 904 897 890 884 878 871 865 859 853 847 842 836 830 825 819 814 808 803 798 793
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Table B.1 TACH Reading Table - Limit2K = `0'
DEC 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 HEX BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB RPM 654 650 647 643 640 637 633 630 627 624 621 617 614 611 608 605 602 599 597 594 591 588 585 582 580 577 574 572 569 566 564 561
Table B.1 TACH Reading Table - Limit2K = `0'
DEC 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 HEX DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB
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Table B.1 TACH Reading Table - Limit2K = `0'
DEC 252 253 254 255 HEX FC FD FE FF RPM 488 486 484 Disabled
RPM 559 556 554 551 549 546 544 541 539 537 534 532 530 527 525 523 521 518 516 514 512 510 508 506 504 502 500 497 495 493 492 490
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